1. Field of the Invention
The present invention pertains to an integrated circuit of the logic circuit type comprising an electrically programmable non-volatile memory. It pertains more specifically to an integrated circuit in which the electrically programmable non-volatile memory consists of an EPROM or EEPROM type memory. Circuits of this type are used, for example, in memory cards also known as CCCs. In this case, the non-volatile memories are most usually designed to receive non-modifiable confidential information which should not be subjected to spurious programming caused by abnormal conditions in the functioning of the card.
2. Description of the Prior Art
Now, in EPROM or EEPROM type memories currently available in the market, each data storage element or memory cell comprises a floating-gate MOS transistor. This type of transistor may have two states. Thus, for an N-channel MOS transistor, in a first state, no charge is trapped at the floating gate. There may be a conduction channel between the source and the drain. The transistor is then conductive and behaves like a closed switch. In a second state, the electrons have been trapped at the floating gate. They prevent the creation of a conduction channel in the substrate between the source and the drain. In this case, the transistor is off and behaves like an open switch.
To programme or read a floating-gate MOS transistor of the type described above, it should be possible to apply several voltages to the various electrodes of the transistor. These voltages are applied by means of read and write circuits controlled by specific signals.
Thus, as shown in FIG. 1, which pertains to an EPROM memory, the memory cell 1 of which consists of a SAMOS (stacked gate avalanche injection MOS) type floating-gate transistor, each floating-gate transistor 1 comprises two main electrodes, 2 and 3 respectively, and a control gate 5 stacked on the floating-gate 4. In the case of a memory, the floating-gate transistors 1 constituting memory cells are connected in matrix form. Thus, a first main electrode 2, or source in the technology used, is connected to a voltage Vss corresponding to the ground while the other electrode 3 or drain is connected by a bits line (not shown) and a MOS transistor 8, which forms a switch, to a column address decoder 7. The control gate 5 is connected by another connection, called a word line (not shown), to a row address decoder 6.
More specifically, the column address decoder 7 is connected to the gate of the transistor 8, having its source connected to the electrode 3 of the floating-gate MOS transistor 1 while its other electrode or drain is connected by a load line, comprising MOS transistors 11 and 12, to the programming voltage Vpp. In fact, the load line is made up of a depleted MOS 11 transistor, the drain of which is connected to Vpp and the source of which is connected to the drain of an enhanced MOS transistor 12, the two gates of the transistors 11 and 12 being connected together and to a write control circuit comprising a NOR gate 13 supplied by the voltage Vpp. The NOR gate 13 respectively receives, at its input, the inverted programming control signal PGM and the inverted datum to be programmed D. The signal D comes from a dynamic register R of a known type. This register R can be used for data storage and data refreshing. More specifically, it receives, at its input, data to be written in the form of the logic level "1" or "0". It comprises essentially storage means formed by capacitors (not shown) designed to be placed before two inverters I1 and I2 and one MOS transistor 14, forming a switch, connected between the output of the inverter I2 and the input of the inverter I1. This transistor is controlled by the signal CLK representing the clock signal of the memory. This MOS transistor 14 is used for data refreshing. Thus, at the output of the inverter I1, namely at the node N', the datum D is obtained and is sent to the input of the NOR gate 13.
Furthermore, the node N between the source of the MOS transistor 12 and the drain of the MOS transistor 8 is connected to a read amplifier represented by the block L.
The functioning of the write circuit described above is essentially dynamic. Thus, the datum D in input of the register R is stored in the form of a load at a high impedance node, and this storage is refreshed regularly by using the clock signal CLK. If this storage is not refreshed, the datum D is lost and the write circuit will behave in a completely unpredictable way. Now, if the integrated circuit is used in memory cards for example, certain zones of the non-volatile memory are reserved, i.e. their writing is strictly checked and most often subjected to the recognition of a secret code. However, with the write circuit described above, if the user sends pulses to the programming voltage Vpp supply, while the voltage Vcc is present but the clock signal CLK is absent, spurious programmings are observed in the non-volatile memory, even in the reserved zones themselves. The reserved zones are then programmed quite randomly.
3. Summary of the Invention
An object of the present invention is to remove these advantages to enable non-supervised writing in an electrically programmable non-volatile memory.
Consequently, an object of the present invention is an integrated circuit of the logic circuit type, comprising an electrically programmable non-volatile memory, consisting of a matrix of memory cells of the floating-gate transistor type, read and write circuits and means to handle the interconnection of these circuits with the memory, the integrated circuit receiving a general supply voltage Vcc, a programming voltage Vpp and an external clock signal divided into two complementary internal clock signals, the said clock signals acting on, among others, the functioning of the write circuits, the said integrated circuit further comprising a circuit to detect the presence of internal clock signals, sending a signal prohibiting write operations in the memory when it detects the absence of one of the internal clock signals.
According to a preferred embodiment, the detection circuit consists of a first circuit comprising a capacitor and a resistor which are parallel mounted between the ground and a common node, the capacitor being regularly charged by means of one of the two internal clock signals, and a second circuit comprising a capacitor and a resistor, parallel-mounted between the ground and a common node, the capacitor being regularly charged by means of the other internal clock signal, the common nodes being connected respectively to each input of a NAND gate, the output of which gives a logic signal indicating the presence or absence of the external clock signal.
Preferably, the output of the detection circuit is connected to the input of a gate, the other input of which receives a signal essential to the write command so as to inhibit the writing operation if the external clock signal is absent.